1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method for fabricating a flash memory device that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern.
2. Discussion of the Related Art
Recently, flash memory devices in common use have been classified into a stacked gate flash cell type and an SONOS (polysilicon-oxide-nitride-oxide-semiconductor) flash cell type. The stacked gate flash cell type has a stack structure including a floating gate and a control gate. The SONOS flash cell type comprises an ONO (oxide-nitride-oxide) gate dielectric and a single gate.
In the stacked gate flash cell type device, a turn-on threshold voltage Vth of the control gate is shifted by a local electric field induced by a hot carrier injected into the floating gate. Programming and erasing functions in the device are based in part on these phenomena.
In the SONOS-type flash memory device, an interface between an oxide layer and a nitride layer in the ONO gate dielectric and an injected hot carrier trap in a defect site of the nitride layer function similarly to the floating gate of the flash memory device having the stacked gate flash cell type.
To improve the operation characteristics of the flash memory device, one should optimize or maximize the hot carrier injection efficiency for programming in the device. Especially, as low power consumption devices are actively researched and developed, the device characteristics for maximizing the hot carrier injection efficiency become more important.
Accordingly, a nonvolatile memory device of the SONOS cell type has attracted great attention in that it can overcome many problems in other nonvolatile memory devices of various cell types.
In the SONOS-type nonvolatile memory device, the top oxide layer functions as a potential barrier for electric charges (e.g., a “gate oxide”). In addition, a new memory trap of high density may be generated at the interface between the top oxide layer and the nitride layer. Accordingly, while maintaining a relatively constant size of a memory window, it is possible to thin a gate insulating layer, specifically, the nitride layer, thereby obtaining a high-efficiency nonvolatile memory device having a programmable voltage for programming and erasing and low power consumption.
Hereinafter, a method for fabricating a flash memory device according to the related art will be described with reference to the accompanying drawings.
FIG. 1A to FIG. 1H are cross sectional views of illustrating the process for fabricating an SONOS type flash memory device according to the related art.
As shown in FIG. 1A, a buffer oxide layer 12 is formed on a mono-crystalline silicon substrate 11. Then, an ion implantation process is performed to form a well in the surface of the semiconductor substrate 11, and a channel ion implantation process for controlling a threshold voltage is performed.
Referring to FIG. 1B, after removing the buffer oxide layer 12, a bottom oxide layer 13 is formed at a thickness between 50 Å and 80 Å on the surface of the semiconductor substrate 11 by LPCVD (low pressure chemical vapor deposition).
Subsequently, a trap nitride layer 14 is stacked on the bottom oxide layer 13 at a thickness between 100 Å and 150 Å by LPCVD. Also, a top oxide layer 15 is grown or otherwise formed on the trap nitride layer 14, wherein the top oxide layer 15 is formed at a thickness between 250 Å and 300 Å by FTP (furnace thermal process).
As shown in FIG. 1C, a conductive material for forming a gate, for example, a polysilicon layer 16 is formed on the top oxide layer 15 at a thickness between 2500 Å and 3000 Å by LPCVD.
As shown in FIG. 1D, the polysilicon layer 16, the top oxide layer 15 and the trap nitride layer 14 are selectively removed by photolithography and RIE (reactive ion etching), thereby forming a gate structure stacking a trap nitride pattern layer 14a, a top oxide pattern layer 15a and a polysilicon pattern layer 16a. Then, a sidewall oxide layer 17 is formed at the side of the trap nitride pattern layer 14a, the top oxide pattern layer 15a and the polysilicon pattern layer 16a. 
As shown in FIG. 1E, a photoresist layer is coated on an entire surface of the semiconductor substrate 11, and then an exposure and development process is performed thereon, thereby defining source and drain regions in the flash memory device. After that, impurity ions are implanted into the surface of the exposed semiconductor substrate 11 in a relatively low concentration and at a relatively low energy.
As shown in FIG. 1F, after implanting the low energy impurity ions, a RTP (rapid thermal process) is performed to form an LDD region 19 and activate the impurity ions. Then, an insulating layer is deposited on the entire surface of the semiconductor substrate 11 and etched back to form a sidewall spacer 20 at the side of the gate.
Subsequently, impurity ions are implanted to the semiconductor substrate 11 in a relatively high concentration and at a relatively high energy, using the sidewall spacer 20 as a mask, thereby forming source and drain regions 21a and 21b. Also, the bottom oxide layer 13 is patterned in alignment with the sidewall spacer 20, thereby forming a tunnel oxide pattern layer 13a. 
As shown in FIG. 1G, a refractory metal layer (for example, cobalt [Co]) 22 is formed on the entire surface of the semiconductor substrate 11, and then a thermal process is performed, whereby the refractory metal layer reacts with the exposed silicon, thereby forming a silicide layer 22a on the surface of the polysilicon pattern layer 16a and on the surface of the source and drain regions 21a and 21b of the semiconductor substrate 11. Then, the non-reacted refractory metal is removed.
As shown in FIG. 1H, an insulating interlayer 23 is formed on the entire surface of the semiconductor substrate 11, and contacts are formed, resulting in plugs 24 for subsequent contact with a metal line.
However, the method for fabricating the flash memory device of the SONOS structure according to the related art has the following disadvantages.
The ion implantation process for forming the source and drain regions using the gate as the mask is performed after forming the gate. As a result, the gate does not overlap with the drain region sufficiently to improve, optimize or maximize the hot carrier injection efficiency at a low power.
Also, because of certain structural problems, it can be difficult to obtain flash memory devices having a size below sub-micron (e.g., less than 0.15 μm, 130 nm, etc.). Furthermore, it can be difficult to improve the programming and erasing speed in the flash memory device.